This invention relates to semiconductor device packages and the method of making such packages and more specifically relates to a chip-scale package and method of its manufacture.
Semiconductor device packages are well known for housing and protecting semiconductor die and for providing output connections to the die electrodes. Commonly, the semiconductor die are diced from a large parent wafer in which the die diffusions and metallizing are made in conventional wafer processing equipment. Such die may be diodes, field effect transistors, thyristors and the like. The die are fragile and the die surfaces must be protected from external environment. Further, convenient leads must be connected to the die electrodes for connection of the die in electrical circuits.
Commonly, such die are singulated from the wafer, as by sawing, and the bottom of the die is mounted on and connected to a portion of a circuit board which has conforming sections to receive respective die. The top electrodes of the die are then commonly wire bonded to other portions of the circuit board, which are then used for external connections. Such wire connections are delicate and slow the mounting process. They also provide a relatively high resistance and inductance.
It is desirable in many applications that the packaged semiconductor devices be mountable from one side of the package, to enable swift and reliable mounting on a circuit board, as well as low resistance connections.
This invention provides a novel semiconductor die package comprising a xe2x80x9cflip-chipxe2x80x9d that is mountable on a circuit board or other electronic interface using one surface of the chip. In particular, the package has contacts, for example, gate, source and drain electrode contacts (for a MOSFET) on the same side of the package, and can be mounted by forming solder ball contacts on the surface of the chip which interface with the external gate, source and drain connections respectively on the circuit board.
The source connection to the chip is made with solder balls on the source electrode of the chip, the solder balls being positioned so that they will interface with appropriate source electrical connections on the circuit board. The package is configured so that the drain electrode is on the same surface.
In one embodiment, the active junctions reside in a layer of relatively low carrier concentration (for example Pxe2x88x92) below the source electrode and above a substrate of relatively high carrier concentration of the same type (for example, P+). At least one drain electrode is positioned on the same surface at a region separate from the source electrode. A diffusion region or xe2x80x9csinkerxe2x80x9d extends from and beneath the top drain electrode, through the layer of relatively low carrier concentration to the substrate. The diffusion region has the same carrier concentration and type as the substrate (for example, P+). Thus, an electrical path is established from the source electrode, through the active elements, and into the substrate, through the diffusion region and to the top drain electrode.
As noted, the drain electrode is on the same surface as the source and gate electrodes and can thus be mounted to the circuit board using solder balls that correspond to locations of appropriate external drain connections.
In another embodiment, instead of using diffusion regions beneath the drain contacts, the layer of relatively low carrier concentration may be etched to the substrate and filled with the drain electrode. This may be done concurrently with the step of etching trenches for a vertical conduction trench-type device, for example.
In a still further embodiment of the invention, two vertical conduction MOSFET devices are formed in a common chip, with their source regions being laterally interdigitated and with a common drain substrate. This structure forms an inherent bidirectional switch. All contacts are available at the top surface, and the contact balls may be located along straight rows which may be symmetrical around a diagonal to a rectangular chip to simplify connection to a circuit board support. The bottom of the chip may have a thick metal layer to provide a low resistance current path between adjacent devices with common drains. It can also improve thermal conduction when the chip is mounted with its top surface facing a printed circuit board support.
Other features and advantages of the present invention will become apparent from the following description of the invention which refers to the accompanying drawings.